A. Field of the Invention
This invention relates to the field of digital data processing systems wherein one or more host data processors utilize one or more supporting scientific processors in conjunction with storage systems that are commonly accessible. More particularly it relates to an improved Scientific Processor tightly coupled to Host Processing System for use in such a digital data processing system. Still more particularly it relates to an improved Scientific Processor having a Scalar Processor Module and a Vector Processor Module, and operable under program control of one or more host processors, and further having addressing compatible with the host processor(s). More particularly, it relates to an improved Scientific Processor tightly coupled for accessing the high speed storage of a host processor(s) without need for dedicated mass storage or extensive caching. Still more particularly, it relates to an improved memory accessing system allowing a tightly coupled Scientific Processor to have access to the virtual address space of the host processor(s).
B. State of the Prior Art
Digital data processing systems are known wherein one or more independently operable data processors function with one or more commonly accessible main storage systems. Systems are also known that utilize a support processor with its associated dedicated supporting, or secondary storage system. Such support processors are often configured to perform specialized scientific computations and are commonly under task assignment control of one of the independently operable data processors. The controlling data processor is commonly referred to as a "host processor". The host processor characteristically functions to cause a task to be assigned to the support processor; to cause required instructions and data to be transferred to the secondary storage system; to cause the task execution to be initiated; and to respond to signals indicating the task has been completed, so that results can be transferred to the selected main storage systems. It is also the duty of the host processor or recognize and accommodate conflicts in usage and timing that might be detected to exist. Commonly, the host processor is free to perform other data processing matters while the support processor is performing its assigned tasks. It is also common for the host processor to respond to intermediate needs of the support processor, such as providing additional data if required, responding to detected fault conditions and the like.
In the past, support scientific data processors have been associated with host data processing systems. One such prior art scientific processor is disclosed in U.S. Pat. No. 4,101,960, entitled "Scientific Processor" and assigned to Burroughs Corporation, of Detroit, Mich. In that system, a single instruction multiple data processor, which is particularly suited for scientific applications, includes a high level language programmable front-end processor; a parallel task processor with an array memory; a large high speed secondary storage system having a multiplicity of high speed input/output channels commonly coupled to the front-end processor and to the array memory; and an over-all control unit. In operation of that system, an entire task is transferred from the front-end processor to the secondary storage system whereupon the task is thereafter executed on the parallel task processor under the supervision of the control unit, thereby freeing the front-end processor to perform general purpose input/output operations and other tasks. Upon parallel task completion, the complete results are transferred back to the front-end processor from the secondary storage system.
It is believed readily seen that the front-end processor used in this earlier system is a large general purpose data processing system which has its own primary storage system. It is from this primary storage system that the entire task is transferred to the secondary storage system. Further, it is believed to be apparent that an input/output path exists to and from the secondary storage system from this front-end processor. Since task transfers involve the use of the input/output path of the front-end processor, it is this input/output path and the transfer of data thereon between the primary and secondary storage systems which becomes the limiting link between the systems. Such as limitation is not unique to the Scientific Processor as disclosed in U.S. Pat. No. 4,101,960. Rather, this input/output path and the transfers of data are generally considered to be the bottleneck in may such earlier known systems.
The prior art also includes array processors coupled to the host processors, but such array processor coupled systems generally require transfers of operands from main storage of the host, to buffers or dedicated storage of the array processor. Characteristically the operational rates of the array processors are considerably faster than the rates of the host and its main storage.
Other data processing systems have included scientific processor(s) coupled to associated general purpose host processor(s) via either input/output (I/O) channels, with the attendant increase in transfer times required in establishing the I/O interconnect; or via shared mass storage such as disks, or rams. These alternative intercouplings require unwanted overhead either in time of establishing link or the required bufferng or caching memories in the scientific processors, or both.
The present scientific data processing system is considered to overcome the data transfer bottleneck by providing unique system architecture using a high speed memory unit which is commonly accessible by the host processor and the scientific processor. Further, when multiple High Performance Storage Units (HPSU) are required, a Multiple Unit Adapter (MUA) is coupled between a plurality of High Performance Memory Units and the Scienfific Processor (SP).
Data processing systems are becoming more and more complex. With the advent of integrated circuit fabrication technology, the cost per gate of logic elements is greatly reduced and the number of gates utilized is ever-increasing. A primary goal in architectural design is to improve the through-put of problem solutions. Such architectures often utilize a plurality of processing units in cooperation with one or more multiple port memory systems, whereby portions of the same problem solution may be parcelled out to different processors or different problems may be in the process of solution simultaneously.
When an SP is utilized in a data processing system to perform supporting scientific calculations in support of a host processor or processors, and is utilized in conjunction with two or more HPSU's, the problem of timing of the access of the SP to any selected HPSU for either reading or writing causes problems of access coordination. In order to coordinate and provide the required control, the over-all system is arbitrarily bounded to require that the SP issue no more than a predetermined number of Requests for access without the receipt back of an Acknowledge. In one configuration, the system is bounded by requiring that no more than eight such Requests be issued by the SP without receipt of an Acknowledge. The details of operation of an SP is set forth in co-pending Application entitled "A Scientific Processor" filed July 31, 1985, as Ser. No. 761,201, how issued as U.S. Pat. No. 4,873,630 on Oct. 10, 1989. The details of the interface and control of a Multiple Unit Adapter for transmitting data to and from a designated HPSU by the SP is described in detail in the co-pending application entitled "Multiple Unit Adapter". The details of operation of the MUA is set forth in detail in copending application entitled "Multiple Unit Adpater" filed Apr. 2, 1984, as Ser. No. 596,205, the parent application (now abandoned) of the continuing application Ser. No. 047,579 filed May 5, 1987, which was issued as patent No. 4,722,052. There it is pointed out that the interface of the HPSU's must also provide for and accommodate different requesters that may be associated therewith. While the data processing system is essentially synchronous, that is operations are under clock control in their execution, the occurrence of Requests, the availability of responding units, and the occurrence of Acknowledge signals are asynchronous with respect to each other. The details of operation of the HPSU's are set forth in detail in the copending application entitled "High Performance Storage Unit", Ser. No. 596,130, filed Apr. 2, 1984, now Patent No. 4,633,434 issued Dec. 30, 1986.
The prior art has recognized that scientific processors generally have computational rates that significantly exceed the storage rates of associated memory systems. This imbalance restricted the use of these earlier systems and made them suitable for only a small class of scientific problems. The previously noted prior art scientific processor disclosed in U.S. Pat. No. 4,101,960 was an exception to that general rule, in that it had a computational rate of one-half of the storage rate of the memory system. A more ideal solution to the problem is to set the maximum rate at which arithmetic/logical computational results are produced in a support processor are approximately equal to the maximum rate that data operands can move to and from the memory system, yielding a computation-to-storage rate ratio that is as close as possible to one-to-one.
Prior art systems have provided for host processor(s) to utilize various types of support (scientific) processor(s), wherein the host processor(s) have access to all of the main memory, but the support processor(s) cannot access all of the main memory. Such arrangements add to system overhead wherein data and/or instructions must be moved by operating system software within main memory to provide access as needed. This results in reduced performance rates of the system. Prior attempts to increase this performance increase, but only at the unacceptable increase in the cost of the system for the performance gained.